1. Field of the Invention
The present invention generally relates to semiconductor memory devices. More particularly, the present invention relates to a semiconductor memory device which can be operated in a test mode for finding a defect of a memory cell configured of a transistor and a capacitor in a dynamic random access memory (hereinafter referred to as a "DRAM").
2. Description of the Background Art
FIG. 31 is a block diagram showing a conventional semiconductor memory device including a plurality of memory blocks. In FIG. 31, to an input terminal 1, input is an address signal, which is applied to an operation block selecting circuit 2, a column address buffer 3, and a row address buffer 4. Operation block selecting circuit 2 provides a block select signal for selecting any memory block. More specifically, the semiconductor memory device is divided into a plurality of memory blocks 11, 12, . . . , 1n, any memory block of which is selected by the block select signal from operation block selecting circuit 2. Memory block 11 includes a column decoder 111, an I/O gate 112, an input/output circuit 113, a row decoder 114, a driving circuit 115, and a memory cell array 116. Other memory blocks 12, . . . , in are configured of the similar components.
Operation block selecting circuit 2 activates column decoder 111 and row decoder 114 when selecting memory block 11, for example. Column address buffer 3 provides an input column address signal to column decoders 111, 121, . . . , 1n1. Row address buffer 4 provides an input row address signal to row decoders 114, 124, . . . , 1n4. Row decoder 114 activates a word line in response to activation of the block select signal of memory block 11 and the row address signal. Then, column decoder 111 designates a column address in response to activation of the block select signal and the column address signal. Data applied through I/O gate 112 from input/output circuit 113 is written in a memory cell of the designated address. Data amplified by a sense amplifier is read out from the memory cell of the designated address, and the data is provided outside from I/O gate 112 through input/output circuit 113.
FIG. 32 is a block diagram showing one example of the row decoder shown in FIG. 31. In FIG. 32, the row decoder includes an inverter 201 inverting the row address signal, and an NAND circuit 202 receiving the row address signal and the inverted row address signal for providing a word line activation signal Xi.
FIG. 33 is a diagram showing one example of the memory cell array shown in FIG. 31. In FIG. 33, the memory cell array includes word lines WL1, WL2, WL3 and bit line pairs BL1, BL1, BL2, BL2 orthogonal thereto. Transistors Q1 to Q6 and capacitors C1 to C6 configuring memory cells are connected to respective crossings of the word lines and the bit line pairs. To bit line pairs BL1, BL1, BL2, BL2, connected are sense amplifier and equalizers 301, 302 for equalizing and precharging the corresponding bit line pair to 1/2 Vcc before data is read out from a memory cell and amplifying a small potential difference after the data is read out.
FIG. 34 is a circuit diagram for explaining operation of transmission of data read out from the memory cell to an I/O line. A row decode signal Xi from row decoder 114 shown in FIG. 32 is applied to a word line driving circuit 115. Word line driving circuit 115 drives a word line WLi in response to a word line drive signal .phi.. Data read out from memory cell array 116 configured of a memory cell transistor Qi and a capacitor Ci to a bit line pair BLi, BLi is amplified by a sense amplifier 303. Sense amplifier 303 includes n channel transistors 311, 312, and p channel transistors 313, 314. Sense amplifier 303 amplifies data read out from memory cell array 116 to the bit line pair BLi, BLi in response to sense amplifier drive signals S2N, S2P. An equalize circuit 304 includes n channel transistors 315, 316 and 317. Equalize circuit 304 equalizes the bit line pair BLi, BLi by a constant voltage V.sub.BL (=1/2.multidot.Vcc) and a bit line equalize signal BLEQ. An I/O gate circuit 305 includes n channel transistors 318, 319 for transmitting a potential of the bit line pair BLi, BLi to an input/output line pair I/O, I/O in response to a column decode signal Yi. The input/output line pair I/O, I/O is pulled up to a level of Vcc-Vth by n channel transistors 320, 321.
FIG. 35 is a timing chart for explaining operation of the circuit of FIG. 34. Referring to FIG. 35, operation of the circuit of FIG. 34 will be described. When the row decode signal Xi attains a logical low level or an "L" level as shown in FIG. 35(a), and the word line drive signal .phi. attains a logical high level or an "H" level as shown in FIG. 35(b), the word line WLi is activated into an "H" level, as shown in FIG. 35(c). At this time, the equalize signal BLEQ is already brought into an "L" level, as shown in FIG. 35(d), and the bit line is already precharged to 1/2 Vcc. Data is read out to the bit line pair BLi, BLi, causing a small potential difference between the bit line pair, as shown in FIG. 35(g), (h). As shown in FIG. 35(e), (f), when sense amplifier drive signals S2N, S2P are activated, the potential difference between the bit line pair BLi, BLi is amplified by sense amplifier 303, as shown in FIG. 35(g), (h) to be a difference between Vcc and Vss levels. Then, the column decode signal Yi is brought into an "H" level as shown in FIG. 35(i). Data amplified by sense amplifier 303 is provided to the input/output line pair I/O, I/O, as shown in FIG. 35(j), (k).
FIG. 36 is a diagram showing a part of the memory cell array shown in FIG. 33. In FIG. 36, memory cell transistors Qi, Qi.sub.+1 and memory cell capacitors Ci, Ci.sub.+1 are connected to respective crossings of the bit line BLi and word lines WLi, WLi.sub.+1. A constant voltage V.sub.cp (=1/2.multidot.Vcc) is applied to one electrode of memory cell capacitors Ci, Ci.sub.+1.
FIG. 37 is a timing chart showing operation in the case where information ("L" level) of the memory cell capacitor Ci connected to the word line WLi shown in FIG. 36 is read out. As shown in FIG. 37(a), when the word 20 line WLi attains an "H" level, the memory cell transistor Qi is turned on, and the information of an "L" level stored in the memory cell capacitor Ci is read out to the bit line BLi through the memory cell transistor Qi, as shown in FIG. 37(c), to be amplified by a sense amplifier, not shown.
When a threshold voltage Vth.sub.i+1 of the memory cell transistor Q.sub.i+1 adjacent to the memory cell transistor Q.sub.i is lower than a design value by any means, as shown in FIG. 37(c), information of an "H" level stored in the memory cell capacitor C.sub.i+1 is gradually leaked to the bit line BLi. When a 16 M-bit DRAM or the like is manufactured, for example, a threshold voltage of a memory cell transistor of several bits is lowered by adhesion of small dust or the like.
In order to exclude a semiconductor integrated circuit including such a memory cell transistor of several bits having a low threshold voltage, a test called disturb refresh test has conventionally been carried out. More specifically, assume that a threshold voltage Vth.sub.+1 of the memory cell transistor Q.sub.i+1 in FIG. 36 is low, for example. Data of an "L" level is written in the memory cell capacitor Ci, and data of an "H" level is written in the memory cell capacitor C.sub.i+1. The data of the memory cell capacitor C.sub.i is repeatedly read out. Since the potential of the bit line BLi to which the memory cell transistor Q.sub.i+1 is connected is at an "L" level, a drain-to-source voltage is generated in the memory cell transistor Q.sub.i+1, causing a subthreshold current to flow. If the threshold voltage Vth.sub.i+1 is low, the subthreshold current is large, and the data is lost. Therefore, data of the memory cell capacitor C.sub.i+1 is read out, and match of the data with the written data is determined. If the data is not matched with the written data, it can be determined that the threshold voltage of the memory cell transistor Q.sub.i+1 is lower than the design value.
When a disturb refresh test is carried out in the blocked DRAM shown in FIG. 31, memory block 11, for example, is selected by operation block selecting circuit 2, and predetermined identical data is written in all the memory cells in memory cell array 116. Then, data continuously activating one word line in memory cell array 116 and connected to a word line adjacent to the one word line is read out, and match of the data with the written data is determined. If they are not matched, it is determined that the threshold voltage of the transistor of the memory cell is lower than the design value. Then, read out is data of a memory cell activating a word line other than the above-described activated word line for a predetermined time and connected to a word line adjacent to the word line, and match of the data with the written data is determined. The operation is carried out for all the memory cells in memory cell array 116.
In a conventional disturb refresh test, word lines are only activated one by one. When a data hold time of cells other than a memory cell connected to a word line adjacent to a particular word line which is continuously activated for a predetermined time is checked, a data hold compensation time of a memory cell is substantially longer than a time required for reading and writing data from and to a cell in general. Therefore, a time required for the disturb refresh test is (the number of word lines).times.(time required for activation of the word lines).times.(the number of blocks which operate simultaneously), when represented without taking into consideration a time required for writing and reading data from and to a memory cell. For example, in the case of a 16 MDRAM, the number of word lines is 16384, a time required for activation of the word lines is 64 msec, and the number of blocks which operate simultaneously is 4. Therefore, a test time required is approximately 262 sec, resulting in a long test time.